1. Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates a method of manufacturing a multiple metallic layered embedded read-only-memory (embedded ROM) that has fewer post-programming processing operations.
2. Description of Related Art
Applications of memories are widespread nowadays. To match the newer generation of lightweight and miniature communication products, the memories used inside must have high memory capacity, small volume occupation and high operating speed. Read-only-memory (ROM) is a type of memory for storing fixed data. ROM has been widely used in digital equipment such as mini-computers and micro-processing system to store fixed programs. The process of manufacturing ROM is rather complicated and involves a large number of steps. The material for carrying out each step must be carefully prepared and all the influencing factors must be properly controlled. Most ROM devices are physically the same except for the codes that need to be programmed in at the programming stage. Therefore, most of steps in the manufacturing of ROM right up to the programming stage can be performed in the factory, forming what is known as a semi-finished ROM product. When a customer sends in an order that requires a particular program, these semi-finished ROM products can be taken out from the warehouse to perform the necessary programming and post-program processing operations. With this arrangement, a turn around time (TAT) is shortened.
As market competition is high, the present trend is to integrate as many functional units onto a single chip as possible. This single chip system capable of performing multiple functions is commonly referred to as a system-on-chip (SOC). Right now, ROM, static random access memory (SRAM), dynamic random access memory (DRAM) logic circuits as well as other digital circuits are mostly fabricated on a single chip so that systems can be more lightweight and can operate faster. Embedded ROM is in fact a common name for these SOC chips.
FIGS. 1A through 1D are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method for producing an embedded ROM unit. First, as shown in FIG. 1A, a substrate 100 is provided. Next, an isolation region 12 is formed in the substrate 10 so that active regions for accommodating memory cells (region 2) and peripheral circuit regions (region 3) are marked out. Thereafter, gate terminal 14 and source/drain regions 22 are formed in the memory cell region 2, and gate terminal 104 and source/drain regions 112 are formed in the peripheral circuit region 3. Hence, a semi-finished embedded ROM unit is formed and ready for programming and post-programming operations.
Next, as shown in FIG. 1B, programming and post-programming operations can start as soon as customer's program code arrives. First, a photoresist layer 24 is formed over the substrate 10, and then an ion implant operation 26 is carried out to form a code region 28.
Next, as shown in FIG. 1C, the photoresist layer 24 is removed, and then a dielectric layer 30 is formed over the substrate 10. Thereafter, metallic interconnect layers 124 are formed in the peripheral circuit region 3. The metallic interconnect layers 124 is formed by forming a contact opening 118 in the dielectric layer 30, and then topping the contact opening 118 with metallic material to form a contact plug 120. Later, a layer of metal is deposited over the dielectric layer 30, and then photolithographic and etching operations are conducted to form a metal line 122.
Next, as shown in FIG. 1D, metallic interconnect layers are formed in the peripheral circuit region 3 as well as the memory cell region 2. The metallic interconnect layers is formed by depositing a dielectric material over the substrate 10 to form a dielectric layer 32. The dielectric layer 32 in the peripheral circuit region 3 and the dielectric layers 30 and 32 in the memory cell 2 region are etched, so that a via hole 132 is formed in the peripheral region 3 and another contact opening (not shown in the figure) is formed in the memory cell region 2. Thereafter, metallic material is deposited to fill the via hole 132 and the contact opening, and then photolithographic and etching operations are conducted to pattern the metallic layer. Ultimately, conductive line 44 is formed over the memory cell region 2 while conductive line 144 is formed over the peripheral circuit region 3. Finally, a passivation layer 48 is formed over the substrate 10 by deposition, hence completing the steps necessary for fabricating the embedded ROM.
However, for the aforementioned method, a number of depositions, photolithographic and etching operations have to be conducted after the arrival of customer's programming code. When there are two levels of metallic interconnection layers in the peripheral region of the ROM, a long turn around time is needed for finish all the processing operations after performing the ion implant operation necessary for coding a customer supplied program into an embedded ROM. As the level of circuit integration continue to increase, more levels of metallic interconnect layers must be used. However, if the conventional method is still used, turn around times of products will have to be extended.